Khóa luận A soft error tolerant sram design in 130nm cmos technology

· This SRAM was designed in 130nm CMOS technology. · Operating voltage range is from 1.35V to 1.65V · Operating frequency is 200MHz (at worst case) · Hand-crafted layout · 22 bit data in/out for SRAM · Only 16 bit data in/out for EDC block interface because the remaining 6 bit data of SRAM were used as parity bit check. · 8 row addresses input and 2 column addresses IO · Two independent clocks for read and write operations as well as two independent data in/out ports and address buses. · Some parts of the design were selected to be radiation hardened · There is also the memory enable control for read and write. · EDC enable pin allows to operate with or without error detection and correction task CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 11 3.1.2. Floorplan MEMORY ARRAY R E F C O L U M N ROW DECODER CONTROL BLOCK R E F I O C E N A REF ROW BUILT-IN EDC BLOCK C E N B A A [0 :9 ] A B [ 0 :9 ] C E N A C E N B C E N A C E N B A A [0 :9 ] A B [ 0 :9 ] C E N A C E N B BUILT-IN EDC BLOCK Q A [0 :2 1 ] D B < 0 :2 1 ] B W E N L A T C H Q I[ 0 :2 1 ] Q I[ 0 :2 1 ] R A M _ M O D E L A T C H S E D E P E R A M _ M O D E D I< 0 :1 5 ] Q O [0 :1 5 ] A B [ 0 :9 ] A A [0 :9 ] C E N B C E N A C E N B C E N A COLUMN MUX SENSE AMPLIFIER - OUTPUT BUFFER Figure 3.1: SRAM floorplan CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 12 3.1.3. Interface pin description Table 3.1: Pin description Pin Name Description CLKA Read port clock input CLKB Write port clock input CENB Write enable CENA Read enable AA Read address AB Write address DI Data in QO Data output RAM_MODE EDC block disable pin · RAM_MODE = 0: the SRAM will work with error detecting and correcting tasks · RAM_MODE = 1: the SRAM will work in normal mode, without error detecting and correcting tasks. DE Double bit error flag SE Single bit error flag PE Parity bit error flag 3.1.4. Operation brief description 3.1.4.1. SRAM operation A write operation is started at the rising edge of CLKB signal. The write enable control input, data input and address input are latched at the beginning of each cycle. During a write operation, data will be written into the memory, and the data will not propagate to the memory output. CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 13 The memory output will remain at the value determined by the last memory read. Figure 3.2: Write operation Similarly, a read operation is started at the rising edge of CLKA signal. The read enable control input and address input are latched at the beginning of each cycle. The data output latch is latched following each read access, controlled by the track path. Figure 3.3: Read operation 3.1.4.2. Built-in EDC operation In each write operation, the 16 bit data input DI of EDC will be encoded to 6 parity bits following the Hamming code. After that, 16 bit data input and 6 parity bits will propagate to 22-bit data in ports DB of the SRAM. That means, in the memory array, only 16 bit is CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 14 data information, the other 6 bits contain the error correcting code, which used to detect and fix the data information if there are errors. In each read operation, the 22 bit data output from SRAM QAwill propagate to the QI of EDC block. EDC will decode 16 bit data output read from the SRAM to six check bits. These six checked bit will be compared with the parity bits read from the memory. If single bit error occurred, EDC would detect and fix. The SE flag will be on and the data output is correct data. If double bit error occurred, EDC would detect but not fix. The DE flag will be on to indicate there is a double bit error. The detail functional of the EDC block will be discussed in EDC architecture section. 3.2. SRAM detail design 3.2.1. SRAM cell architecture This SRAM cell was applied the circuit hardening technique [11, 12]. Some extra transistors were adding to the classic 8 transistors SRAM cell. In detail, two additional inverters and a control transistor are included as in figure below. The control transistor is ON when both RWL and WWL are low. Therefore, this extra protection circuit is only turned on in standby mode. During the standby mode, the extra transistors will be used to enhance the charge value of IBL and IBLX, which lead to increase the critical charge value of these nodes. That means, the soft error tolerant level of this SRAM cell is improved. The level of soft error tolerant depends a lot on the physical parameter and characteristic of the extra transistors. CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 15 Figure 3.4. SRAM cell architecture Because the protection circuit is OFF during normal mode (read/write), it will not affect a lot the read and write performance. The level of soft error tolerant depends a lot on the physical parameter and characteristic of the extra transistors. Increasing width of extra transistor could enhance the tolerance level; however, this will trade off with the area overhead. 3.2.2. Replica path for Read operation WWL WWL RWL RWL PENX PENX WBL WBL RBL RBL WBLX WBLX IBLX IBL Figure 3.4: SRAM cell architecture CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 16 This design uses the inverter sense; the output latch is enabled by the signal obtained from the reference column and reference row. Reference column is an additional column used to generate the enabling signal for the output latch. It has 256×1 bits and the same bitline capacitance as that in the cell array. Reference row is an additional row used to generate the reference read wordline signal which reads the cells in reference column. This additional row makes the reference read wordline have the same capacitance as that for wordlines in cell array. The reference row and column are configured to model the furthest path of the array. Therefore, ensure that the output latch is opened after the data read from memory valid. The reference column cell, reference row cell, reference feedback row cell are the edition of the memcell. In the reference column cell, the “pull up” pmos transistors are disconnected from the IBL because these cells are just used to model the bitline capacitance. In the reference row cell, IBL, IBLX and DMWWL are shorted together while DMWWL is tied to VSS at XDEC block. The reference feedback row cell is put at the middle of the array. The DMRWLFB signal is enabled when DMRWL reaches to the feedback cell. In the reference memcell, IBL and IBLX are tied to high. DMXDEC XDEC CTL XDEC REFMEM REFROW REFROWFB REFROW … … … REFCOL MCELL MCELL MCELL … … REFCOL MCELL MCELL MCELL … … … IOREF IO IO IO CPGEN VC P LATCH DMRWL DMRWLFB D M RB L ECHO CLKA Out latch Out latch Out latch QA[0] QA[21] QA[n] Figure 3.5: Timing scheme for read operation CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 17 During the read operation, both the accessed RWL and the reference RWL go high. The reference_row_feedback cell enables the DMRWLFB, leads to a read 0 operation at the reference memcell. The DMRBL is discharged, opens the output latch, and also sends the echo signal back to reset internal clock. Figure 3.6 above shows the schematic of reference IO cell and the read circuit in IO cell. In the cycle low, the DMRBL is pre-charged. When the read operation is initiated, a read 0 from reference memcell will discharge the DMRBL. Therefore, send the signal to open the output latch of the read circuit in the IO cells, the read data then propagate to output port. The output latch is closed by the falling edge of internal read clock to keep the value of data out. 3.2.3. Internal clock generator 3.2.3.1. Read clock generator circuit LATCH Mux select RMSE RMSE RB L< 0: 3> RHCPX Output latch Figure 3.6: Reference IO cell and read circuit CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 18 A read operation is starting by the rising edge of CLKA. Signal PULDOWN is delayed from CLKA to pull the INTCLKX down to VSS. Rising edge on LCP pulse is sent to IO block to start a read operation. As mention in the 3.2.2 section, when the DMRBL is discharged, an echo signal will be sent back to read clock generator circuit, indicate that the high level duration of read clock is enough for a read operation, then the LCP signal will be reset (RESETX goes low). This will be sent to the IO block to close the output latches. After when the LCP is reset, the feedback signal (HCPFB) will come back to disable the reset signal (RESETX goes high). Then it is ready to start a new read cycle. HCPFB RESETX Figure 3.7: Read clock generator circuit CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 19 3.2.3.2. Write clock generator circuit There are two main control pulses generated from write clock generator circuit. One is the WVCP which goes to XDEC block to open the WWL. The other is WHCPX which goes to IO block to control the write operation. 3.2.4. Write circuit Figure 3.9 below is the write circuit and its sequential waveform. The data will be written to the memory array when both write clock (WCP) and mux select (WMSE) enable. A write 0 operation will pull down the WBL while a write 1 will pull down the WBLX. Both the read and write circuit are included in the IO cell. e 3.2.5. Decoder · Row Decoder Figure 3.9: Write circuit and sequential waveform Figure 3.8: Write clock generator CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 20 An 8-256 decoder which decodes the higher 8 address inputs (A2-A9) to select the accessed row. There are two decoding outputs for each row, Write WordLine (WWL) and Read WordLine (RWL), active during write and read operation respectively. The decoder is implemented as following block diagram to improve area and performance. Figure 3.11 below shows the circuit of XDEC bloc. The TGATE is enabled when this row is selected by the 2_to_8 decoder. When the read or write control pulse goes high (RVCP/WVCP), the read or write word line will be opened. The PENX which enable the protection circuit in SRAM cell will go low (PENX active low) when both RWL and WWL is disabled. 2_dec_4 A< 2> A< 3> PA 0 PA 1 PA 2 PA 3 2_dec_4 A< 4> A< 5> PB 0 PB 1 PB 2 PB 3 2_dec_4 A< 6> A< 7> PC 0 PC 1 PC 2 PC 3 2_dec_4 A< 8> A< 9> PD 0 PD 1 PD 2 PD 3 WWL RWL XDEC_0 PA0 PB0 PC0 PD0 A B C D WWL RWL XDEC_1 PA1 PB0 PC0 PD0 A B C D WWL RWL XDEC_255 PA3 PB3 PC3 PD3 A B C D ..… Figure 3.10: Row decoder block diagram CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 21 The TGATE is enabled when this row is selected by the 2_to_8 decoder. When the read or write control pulse goes high (RVCP/WVCP), the read or write word line will be opened. The PENX which enable the protection circuit in SRAM cell will go low (PENX active low) when both RWL and WWL is disabled. · Column Decoder: A 2-4 decoder which decodes the lower 2 address inputs (A0-A1) to select the accessed column. 3.2.6. Input/output latches Just like the SRAM cell, the latches are parts that easily suffer from SEU. Latches are used at address input, data input and data output. Opening latch will let data go through, however, when closed; data will be stored in latch. A SEU could flip the state of data stored in latch, lead to an erroneous data. Therefore, in this SRAM design, latches are hardened to duplicate some sensitive nodes. All the latches in the design, include address input latch, data input latch and output latch are applied this techniques. WWL RWL PENX Figure 3.11: Xdec circuit CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 22 Figure 3.12: Hardened latch architecture The hardened latch architecture is shown in the figure 3.12 above. In this latch architecture, each sensitive node is strengthened by adding more transistors. For example, node DX1 is the duplication of node DX2. This is done by the two additional transistors, N2 and P2, similarly for node Q1 and Q2. So, if a SEU occurred at the DX2 branch, then the data will be saved by the DX1 branch. The feedback circuit which is enabled when closing latch is also divided in two, the above one is used to feedback the ‘1’ value while the below one is used to feedback the ‘0’ value. With this latch architecture, the soft error tolerant level could be increased significantly. 3.3. Error detecting and correcting (EDC) block The EDC block used the Hamming code algorithm[10, 13] to implement the error correcting code. The EDC block encodes all data bits into parity bits to be written N2 P2 Q1 Q2 CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 23 into memory during write operation. During the read operation, it evaluates these parity bits to detect if the data bits are erroneous. For single bit error detected, EDC can flag and correct while it can only flag if there is a double bit error. 3.3.1. Hamming code algorithm Do the following step to have a visual view about the Hamming code algorithm: · Step 1: Number the bits starting from 1: bit 1, 2, 3, 4, 5, etc. · Step 2: Write the bit numbers in binary. 1, 10, 11, 100, 101, etc. · Step 3: All bit positions that are powers of two (have only one 1 bit in the binary form of their position) are parity bits. · Step 4: All other bit positions, with two or more 1 bits in the binary form of their position, are data bits. · Step 5: Each data bit is included in a unique set of 2 or more parity bits, as determined by the binary form of its bit position. o Parity bit P0 covers all bit positions which have the least significant bit set: bit 1 (the parity bit itself), 3, 5, 7, 9… o Parity bit P1 covers all bit positions which have the second least significant bit set: bit 2 (the parity bit itself), 3, 6, 7, 10, 11, … o Parity bit P2 covers all bit positions which have the third least significant bit set: bits 4–7, 12–15, 20–23 … o Parity bit P3 covers all bit positions which have the fourth least significant bit set: bits 8–15, 24–31, 40–47 … o Parity bit P4 covers all bit positions which have the fifth least significant bit set: o The parity bit P5 is the special bit which covers all bit position, the purpose is to distinguish the error is single bit or double bit Following table is the example of 22 encoded bits which were applied for 22k SRAM. CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 24 Table 3.2: Hamming code for 22 bits Bit position Bit position in binary Encoded data bits Parity bit coverage P0 P1 P2 P3 P4 P5 1 001 P0 x 2 010 P1 x 3 011 D0 x x x 4 100 P2 x 5 101 D1 x x x 6 110 D2 x x x 7 111 D3 x x x x 8 1000 P3 x 9 1001 D4 x x x 10 1010 D5 x x x 11 1011 D6 x x x x 12 1100 D7 x x x 13 1101 D8 x x x x 14 1110 D9 x x x x 15 1111 D10 x x x x x 16 10000 P4 x 17 10001 D11 x x x 18 10010 D12 x x x 19 10011 D13 x x x x 20 10100 D14 x x x 21 10101 D15 x x x x It can be seen from the table that any given data bit is included in a unique set of parity bits. To check for errors, check all of the parity bits. The parity bit P5 will indicate whether it is a single or double bit error. The remaining parity bit will determine the bit position if it is a single bit error. For example, D0 is included in the unique set of P0 and P1, so if D1 is the erroneous bit, then the parity bit P5, P0 and P1 value will be different with the original. Parity P5 shows that there is a single bit error and P0 and P1 identify the erroneous bit is D0. 3.3.2. EDC block implementation CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 25 3.3.2.1. Block diagram 3.3.2.2. EDC operation using Hamming code algorithm The Hamming code algorithm is implemented for 22 k SRAM as following: · During the write operation, 16 data input bit are encoded to 6 parity bits P by XOR operator with the checkpoint in the table 3.2. Then the W RI TE E N CO D ER RE A D D EC O D ER P AR IT Y CO M PA RA TO R SY N D RO M E D EC O D ER BI T FL IP PE R EDC BLOCK DI <0 :1 5> P< 0: 5> D I< 0: 15 > D E PE SE Q O <0 :1 5> Q I< 0: 21 > Q I< 0: 15 P< 0: 5> Q I< 0: 15 > Q I< 16 :2 0 > Q I< 16 :2 1 > P< 0: 5> PD PO FEN D I< 0: 21 > READ and PARIRY DECODER Q I< 0: 15 > D< 0: 15 > O U TP U T SE LE CT O U TP U T SE LE CT Q <0 :1 5> LATCH LATCH VSS RAM_MODE RAM_MODE RA M _M O DE RA M _M O DE LA TC H Figure 3.13: EDC block diagram CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 26 total 22 bit (data and parity bits) are written to the memory array (the six right bits of the memory array used to store the parity bit information) · During the read operation, 16 data output bit will be decoded to 6 check bits PD by XOR operator like in write operation. Note that the PD is the XOR operation of all data output bit and parity bit P read from memory. · Compare P and PD by XOR operator: PO = XOR{P, PD} o If PO = 1, single bit error occurred, SE flag will be ON § If PO=0, the single bit error is one of the parity bit from P0 to P4. The PE flag will be ON § Otherwise, the single bit error is one of the data bit. The error bit position is determined by equation Error Bit position = PO x 24 + PO x 23 + PO x 22 + PO x 21+ PO x 20 o If PO = 0 and PO result in a non zero value, then the double bit error occurred, DE flag will be on o If single bit error occurred, the error bit will be flipped. o If P = 0, there are no error. 3.3.3. EDC detail architecture 3.3.3.1. Write encoder The write encoder block uses the XOR operation to encode 16 data bit inputs to six parity bits following the Hamming code algorithm CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 27 Following the Hamming code algorithm in table 3.2, the parity bits are encoded as below: P0 = XOR{ D0, D1, D3, D4, D6, D8, D10, D11, D13, D15} P1 = XOR{ D0, D2, D3, D5, D6, D9, D10, D12, D13} P2 = XOR{ D1, D2, D3, D7, D8, D9, D10, D14, D15} P3 = XOR{D4, D5, D6, D7, D8, D9, D10} P4 = XOR{D11, D12, D13, D14, D15} P5 = XOR{D, P} 3.3.3.2. Read decoder The read decoder decodes 16 data output to 6 check bits PD by XOR operator like in write encoder. Note that the PD is the XOR operation of all data output bit and parity bit P read from memory, which are now the QI output from the memory. Please refer to figure 3.13. The read decoder schematic is also similar to the write encoder schematic. D0, D1, D3, D4, D6, D8, D10, D11, D13, D15 SRAM_XOR10 D Y P0 SRAM_XOR7 D Y P3 D D0, D2, D3, D5, D6, D9, D10, D12, D13 SRAM_XOR9 D Y P1 SRAM_XOR5 D Y P4 D D, D, D SRAM_XOR9 D Y P2 SRAM_XOR21 D Y P5 D, P Figure 3.14: Write encoder schematic CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 28 3.3.3.3. Parity comparator It could be summarized as following: · P is the XOR operation of all data input bit and parity bit P before being written to memory. · PD is the XOR operation of all data output bit and parity bit P read from memory In which parity bits P are encoded from data input bit Therefore, comparing the P and PD will help determine the error is single or double bit. The comparison of the remain bits indicate the single bit error position PO = XOR{P, PD} Figure 3.15: Parity comparison schematic 3.3.3.4. Syndrome decoder CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 29 Figure 3.16: Syndrome decoder schematic · If PO = 1, single bit error occurred, SE flag will be ON, the FEN signal will be sent to enable the flipping bit task. o If PO=0, the single bit error is one of the parity bit from P0 to P4. The PE flag will be ON o Otherwise, the single bit error is one of the data bit. · If PO = 0 and PO result in a non zero value, then the double bit error occurred, DE flag will be on 3.3.3.5. Bit flipper As can be seen in the table 3.2, any given data bit is included in a unique set of parity bits. Therefore, a 3to8 decoder and a 2to4 decoder are used to decode the comparison bits to find the erroneous bit position. The erroneous bit will be then flipped the state (0 to 1 or 1 to 0) by the bit flipper block. CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 30 3.3.3.6. EDC input/output select and output latch a. Input select RAM_MODE is the EDC block disable pin. If RAM_MODE = 0, the SRAM will work with error detecting and correcting tasks. Otherwise, the SRAM will work in normal mode, without error detecting and correcting tasks. Therefore, during the write operation, RAM_MODE pin acts as the bit write enable pin for six right data input bits. If RAM_MODE = 0, all 22 data bit (16 bit data and 6 bit parity encoded from the write encoder of EDC block) will be written to the memory array. If RAM_MODE = 1, the bit write pin for six right input bits of SRAM is disabled, and only 16 bit data are written BIT FLIPPER 3_DEC_8 P2 P1 P0 PS2 PS1 PS0 PS5 PS4 PS3 PS7 PS6 2_DEC_4 P1 P0 PS2 PS1 PS0 PS3 PO2 PO1 PO0 PO3 PO4 BIT_FLIPPER_0 Q PS1 PS2 FEN DO D FEN D BIT_FLIPPER_15 Q PS1 PS2 FEN DO D FEN D … .. Figure 3.17: Bit flipper block CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 31 to memory array, the six right column of the memory array are then not affected. b. Output select and output latch Each data output bit (QO and notification flags SE, PE, DE) must go through an output select circuit and output latch before going to the output ports. Depending on the RAM_MODE pin status, the output select circuit will select which data can go to the output port. For the notification flags, if RAM_MODE = 1, means no correction tasks occur, all the flags will be tied to VSS. In contrast, when RAM_MODE = 0, the flags will get the value returned from the syndrome decoder block. For the output data, if RAM_MODE = 1, means no correction tasks occurred, the output data will be got directly from the SRAM output. In contrast, when RAM_MODE = 0, the output data is the data which are decoded and corrected. IO cells for six right bits with bitwrite enable pin Figure 3.18: Input select CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 32 Figure 3.19: Output select and output latch All the output bits are also latched by LATCH signal. This LATCH signal is obtained from the output latch signal of SRAM, however, plus a delay to model the delay of data output when passing through the EDC block. This latch is also the hardened latch mentioned in section 3.2.6. Out_latch CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 33 3.4. Physical implementation 3.4.1. Top level design layout view The memory top layout view is partitioned just like the floorplan presented in section 3.1.2. All the input pins are placed at the bottom of the memory. EDC block Memory Array IO Control Xdec RR ee f f ee rr ee nn cc ee ii oo RR ee f f ee rr ee nn cc ee cc oo ll uu mm nn Figure 3.20: Top level layout view CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 34 3.4.2. Memory cell layout Figure 3.21: SRAM cell layout with only device layers shown The SRAM cell has been drawn to minimize the area and try to have smoothly shapes for all layers. There is no strap cell included in SRAM cell to save the area. The strap cell is inserted in each 36 rows. Two SRAM cell will share the same power line. The wordline and protection enable signal are drawn in metal 3 while the bitline signals are drawn in metal 2. This SRAM cell area is 10.35 um2. 3.4.3. Layout view of other block Figure 3.23: Xdec cell layout RWL PENX RB L VS S VD D W BL W BL X Width = 5.75 um, Height = 1.8um, Area = 10.35 (um2) WWL Layer Panel The share power line in m3 Figure