Outline
I. Introduction . 3
II. Content
1. Unix, C Shell, Perl . 4
1.1 What's Unix?.4
1.2 Kernel .4
1.3 Shell.4
1.4 C shell.6
1.5 Perl.9
2. CMOS Technology . 10
3. Logic gate and simulation. 14
1.1 INV gate.15
1.2 INV_Z gate.18
1.3 AND2 gate.19
4. Memory design overview . 20
5. Project: Design 4 to 16 Decoder. 24
III. Conclusion . 29
IV. Referential Documents . 30
31 trang |
Chia sẻ: maiphuongdc | Lượt xem: 1798 | Lượt tải: 1
Bạn đang xem trước 20 trang tài liệu Báo cáo CMOS Circuit Design and Simulation, để xem tài liệu hoàn chỉnh bạn click vào nút DOWNLOAD ở trên
University of Science Silicon Design Solution
Faculty of Electronics and Telecommunications A Division of eSilicon
-----*------
Internship report
CMOS Circuit
Design and Simulation
Reporter : Pham Ngoc Loi
Student ID : 0720142
Tutors : Hoang Le Tan Dung
Nguyen Truong Kha
Nguyen Duc Thien Son
Ho Chi Minh city - Jan 2011
Internship report
1
Comment of company and tutors
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
................................................................................................................................................
Internship report
2
Outline
I. Introduction............................................................................................. 3
II. Content
1. Unix, C Shell, Perl ..................................................................... 4
1.1 What's Unix?...............................................................................4
1.2 Kernel .........................................................................................4
1.3 Shell..............................................................................................4
1.4 C shell..........................................................................................6
1.5 Perl........................................................................................9
2. CMOS Technology.................................................................... 10
3. Logic gate and simulation.......................................................... 14
1.1 INV gate......................................................................................15
1.2 INV_Z gate..................................................................................18
1.3 AND2 gate...................................................................................19
4. Memory design overview .......................................................... 20
5. Project: Design 4 to 16 Decoder................................................ 24
III. Conclusion .............................................................................................. 29
IV. Referential Documents .......................................................................... 30
Internship report
3
I. Introduction
Circuit design is one of the most important level of CMOS IC design. The
performance of CMOS ICs depend on the quality of circuit design. Circuit design
includes designing and simulation. Simulating the design shows us the waveform of
the circuit, delay, DC, AC characteristics. Moreover, we can vary parameters of
circuit to check the operation in different conditions; from this variation, we can find
out the best parameters for our design.
I want to thank SDS company who gave me a chance to practice at company; I
thank Mr. Ho Nam Tinh, Mr. Hoang Le Tan Dung, Mr. Nguyen Truong Kha and Mr.
Nguyen Duc Thien Son for their help. I also want to thank my teachers in University
of Science; specially, I want to thank Mr. Huynh Huu Thuan who always inquires
after his students.
Internship report
4
Unix, C shell, Perl
1.Unix:
1.1 What's Unix?
• UNIX is a computer operating system originally developed in 1969 by a group of
AT&T employees at Bell Labs.
• Today’s UNIX system are splited into various branches, developed over
time by AT&T as well as various commercial venders and non-profit
organizations.
• Today, in addition to certified UNIX systems, UNIX-like operating system
such as Linux and BSD are commonly encountered.
1.2 Kernel
• Kernel is the central component of the most operating system. Its
responsibilities include managing the system’s resources (the communication
between software and hardware components).
• As a basic component of an operating system, a kernel provides the
lowest-level abstraction layer for the resources (especially memory,
processors and I/O devices) that application software must control to
perform its function.
1.3 Shell
• Shell acts as an interface between user and kernel.
• As a UNIX user, you have a choice of shells available to you. These are the
Bourne shell, the C shell, the Korn shell.
1.3.1 The directory structure
• All the files in UNIX are grouped together in the directory structure. The file-
system is arranged in a hierarchical structure, like an inverted tree. The top of the
hierarchy is traditionally called root (written as a slash /).
• Example of directory structure:
Internship report
5
1.3.2 Basic command
• Basic commands in UNIX are: mkdir, cd, cp, mv, rm, cat, touch, vi, ls, du, df,
pwd, who, id, chmod, chown, chgrp, top, rlogin, rsh, ssh, ftp, sftp, clear, echo,
setenv, tar, gzip, kill, history, man.
o mkdir: create directory.
o cd: change directory.
o mv: move or rename a file or directory.
o rm: remove file or directory.
o cat: concatenate files and print on the standard output.
o touch: create blank file.
o vi: start text editor.
o ls: list directory contents.
o pwd: print name of current/working directory.
o du: estimate file space usage.
o df: report filesystem disk space usage.
o who: show who is logged on.
o id: print real and effective UIDs and GIDs.
o chmod: change file access permissions.
o chown: change file owner and group.
o chgrp: change group ownership.
o top: display Unix/Linux tasks.
o rlogin: remote login.
o rsh: remote shell.
o ssh: OpenSSH SSH client (remote login program).
o ftp: file transfer program.
o sftp: secure file transfer program.
o clear: clear the terminal screen.
o echo: display a line of text.
o setenv: add or change environment variable.
o tar: the GNU version of the tar archiving utility.
o gzip: compress or expand files.
o kill: terminal a process.
o history: the history command performs one of several operations.
o related to recently-executed commands recorded in a history list.
o man: format and display the on-line manual pages.
For more detail about above commands, from terminal, type: man
1.3.3 Vi editor
• The VI editor is a screen-based editor used by many Unix users.
• Some simple VI commands.
Internship report
6
1.4 C shell
1.4.1 About C-shell
• The C shell (csh) is a developed by Bill Joy for the BSD Unix system. It was
originally derived from the 6th Edition Unix /bin/sh (which was the Thompson
Shell), the predecessor of the Bourne Shell. Its syntax is modeled after the C
programming language. The C shell added many feature improvements over the
Bourne shell, such as aliases and command history. Today, the original C shell is
not in wide use on Unix; it has been superseded by other shells such as the Tenex
C shell (tcsh) based on the original C shell code, but adding filename completion
and command line editing, comparable with the Korn Shell (ksh), and the GNU
Bourne-Again shell (bash).
• The C shell has the typical Unix shell structure: each line of input (or line of a
script file) is interpreted as a separate command to execute, with backslashes
"escaping" newlines where needed (so that multiple input lines can comprise a
single command to be executed).
Internship report
7
1.4.1 Invoking C-Shell
• Each time you log in to UNIX, you're placed in an interactive shell referred to
as your login shell. If your login shell is C shell, you can tell by its command-line
prompt: the percent sign (%). The C shell prompt differs from the dollar sign
prompt ($) of the Bourne shell to remind you that you're using the C shell.
• If your login shell is not C shell, and C shell is available on your system, you
can invoke it as an interactive shell from the command line. Even when you're
already running the C shell, there will be times when you want to launch the C
shell again, for example to run a shell script or to temporarily change the shell's
options. To invoke the C shell interactively, use the following command:
$ csh
%
1.4.2 Built-in shell command
Internship report
8
Internship report
9
1.4.3 Example a Shell program
1.4.Perl
What's Perl?
• Perl is the power and flexibility of high-level programming languages .
• Contain control structures and operators similar to C programming.
• Ability to write useful programs in a very short time.
• Perl is freeware.
Perl scrip
• A Perl program consists of an ordinary text file containing a series of Perl
commands.
• Ex:
#!/usr/local/bin/perl
print “Hello world!\n”;
Internship report
10
CMOS TECHNOLOGY
The MOS Transistor
Switch model of NMOS Transistor
The NMOS Transistor Cross Section
n areas have been doped with donor ions (arsenic) of concentration ND -
electrons are the majority carriers .
p areas have been doped with acceptor ions (boron) of concentration NA -
holes are the majority carriers
Internship report
11
Switch model of PMOS Transistor
Gate oxide
n+
Sourc Drain
p substrate
Bulk (Body)
p+ stopper
Field-Oxide
(SiO2) n+
Polysilicon
Gate
L
W
Gate
Source
(of carriers)
Drain
(of carriers)
| VGS |
| VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| |
Open (off) (Gate =
‘1’)
Closed (on) (Gate =
‘0’) Ron
Internship report
12
Threshold voltage
The value of VGS where strong inversion occurs is called the threshold voltage,
VT:
VT = VT0 + γ(√|-2φF + VSB| - √|-2φF|)
where
o VT0 is the threshold voltage at VSB = 0 and is mostly a function of the
manufacturing process.
o VSB is the source-bulk voltage.
o φF = -φTln(NA/ni) is the Fermi potential (φT = kT/q = 26mV at 300K is the
thermal voltage; NA is the acceptor ion concentration; ni ≈ 1.5x1010 cm-3 at
300K is the intrinsic carrier concentration in pure silicon) .
o γ = √(2qεsiNA)/Cox is the body-effect coefficient (impact of changes in VSB)
(εsi=1.053x10-10F/m is the permittivity of silicon; Cox = εox/tox is the gate
oxide capacitance with εox=3.5x10-11F/m).
Short channel effect
Behavior of short channel device mainly due to
Velocity saturation – the velocity of the carriers saturates due to
scattering (collisions suffered by the carriers)
For an NMOS device with L of .25µm, only a couple of volts
difference between D and S are needed to reach velocity saturation
Voltage-Current Relation: Velocity Saturation
For short channel devices
Linear: When VDS ≤ VGS – VT
ID = κ(VDS) k’n W/L [(VGS – VT)VDS – VDS2/2]
Internship report
13
where κ(V) = 1/(1 + (V/ξcL)) is a measure of the degree of velocity saturation
Saturation: When VDS = VDSAT ≥ VGS – VT
IDSat = κ(VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT2/2]
Short Channel I-V Plot (NMOS)
Internship report
14
Logic Gate and Simulation
1.1 INV gate
Switching Threshold:
Variation in device ratio:
With : FF process, W = 0.12, L = 0.04, temp = 0, Vsup = 0.8V
(W/L)p/(W/L)n
Vtrip
%VDD
Delay
1 3.8627
0.416
-2.1p
2 3.8089
0.448
-2.77p
3 3.8295
0.476
-2.60p
4 4.0047
0.502
7.04p
Process variation
With : W = 0.12, L = 0.04, temp = 0, Vsup = 0.8V
Process
Vtrip
%VDD
Delay
FF
3.8627
0.483
-2.1p
FS
3.3275
0.416
-10p
TT
4.1513
0.519
2.3p
SF
4.9682
0.621
1.49p
SS
4.9778
0.622
1.47p
Internship report
15
Netlist
- subckt:
describe sub circuit of the circuit; in this command, we list input and output pins of the
sub circuit; if sub circuit has parameters, we have to list their parameters in this
command.
- xi: describe instance circuit of a sub circuit.
Internship report
16
Schematic
Simulation and delay
Internship report
17
1.2 INV_Z gate
Schematic
Simulation
Internship report
18
1.3 AND2 gate
Schematic
Simulation
Internship report
19
Memory design overview
1. The 1-bit Binary Adder:
Truth table
A B Cin Cout S carry status
0 0 0 0 0 kill
0 0 1 0 1 kill
0 1 0 0 1 propagate
0 1 1 1 0 propagate
1 0 0 0 1 propagate
1 0 1 1 0 propagate
1 1 0 1 0 generate
1 1 1 1 1 generate
From the truth table above, we find out the output equations:
G = A&B
P = A ⊕ B
K = !A & !B
S = A ⊕ B ⊕ Cin
Cout = A&B | A&Cin | B&Cin (majority function)
Schematic of the 1-bit Binary Adder
A B
S
Cout
Cin
schematic at logic gate level
Internship report
20
Cout
S
Cin
A
B
schematic at transistor level
2.Memory Cell:
RWM:
Random Access: SRAM( cache, register file), DRAM.
Non- Random Access: FIFO/LIFO, Shift Register, CAM.
NVRWM:
EPROM, E2PROM, FLASH.
ROM:
Mask-programmed, Electrically-programmed (PROM).
Internship report
21
1D Memory Architecture:
Word 0
Word 1
Word 2
Word n-1
Word n-2
Storage
Cell
m bits
S0
S1
S2
S3
Sn-2
Sn-1
Input/Output
A0
A1
Ak-1
De
co
der
Decoder reduces # of inputs
k = log2 n
Internship report
22
2D Memory Architecture:
A0
Row
Dec
oder
A1
Aj-1 Sense Amplifiers
word line
storage
(RAM) cell
Row
Add
ress
Column
Address
Aj
Aj+1
Ak-1
Read/Write Circuits
Column Decoder
2k-j
m2j
Input/Output (m bits)
amplifies bit line swing
Internship report
23
SRAM circuit
Static – SRAM and Dynamic – DRAM:
Static – SRAM Dynamic – DRAM
+data is stored as long as supply is applied
+large cells (6 fets/cell) – so fewer bits/chip
+fast – so used where speed is important
(e.g., caches)
+differential outputs (output BL and !BL)
+use sense amps for performance
+compatible with CMOS technology
+periodic refresh required
+small cells (1 to 3 fets/cell) – so more bits/chip
+slower – so used for main memories
+single ended output (output BL only)
+need sense amps for correct operation
+not typically compatible with CMOS
technology
Internship report
24
4 to 16 decoder
Overview
• Design 4 to 16 decoder, using basic logic gate: nand2, nor2, inv.
• Simulate and view waveform.
• Apply to:
Design
• State table:
Word
0 Word
1 Word
2
Word n-
1
Word n-
2
Storage
Cell
m
bits
S0
S1
S2
S3
Sn-2
Sn-1
Input/Output
A0
A1
Ak-1
De
co
der
Internship report
25
• Use bool expression and De Morgan statement, we have:
o Y0 = DCBA ... = ( )( )DCBA ++ .
o Y1 = DCBA ... = ( )( )DCBA ++ .
o Y2 = DCBA ... = ( )( )DCBA ++ .
o ...
Schematic
• Y0
Internship report
26
• Y1
• Y2
• .....
• ....
• 4 to 16 decoder
Internship report
27
Internship report
28
Waveform
Internship report
29
III.Conclusion
So I think, in SDS, I learned a lot of useful things to supplement my knowledge in
university and prepare for my future job.
One more time, I want to thank to SDS and all people who give me useful help!
Internship report
30
IV.Referential Documents
Unix_C-shell_perl_training_document, Septemper 15, 2008 author Le Tu Duc.
Slide Powerpoint SDS_100, January 25th 2008.
SE_LAPs documents.
Hspice_sa.pdf, version D-2010.03, March 2010
Các file đính kèm theo tài liệu này:
- report_loi.pdf